发明名称 |
Logic Chip, Logic System and Method for Designing a Logic Chip |
摘要 |
A logic chip has a plurality of individually addressable resource blocks each of the resource blocks having logic circuitry, and a communication bar extending across a plurality of the individually addressable resource blocks. The communication bar has a plurality of communication bar segments associated with the resource slots. The communication bar segments of the individually addressable resource blocks have identical interface locations with respect to boundaries of the resource blocks, such that an input interface location of a first resource block matches an output interface location of an adjacent second resource block. At least one of the individually addressable resource blocks has a bypass segment of the communication bar. At least one of the individually addressable resource blocks has an access segment of the communication bar. The access segment has an access structure inserted between a first communication bar interface location and a second communication bar interface location, to allow for a read access or a write access or a combined read/write access to the communication bar.
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申请公布号 |
US2010283505(A1) |
申请公布日期 |
2010.11.11 |
申请号 |
US20080677474 |
申请日期 |
2008.09.08 |
申请人 |
FRIEDRICH-ALEXANDER-UNIVERSITAET-ERLANGEN- NUERNBERG |
发明人 |
KOCH DIRK;STREICHERT THILO;HAUBELT CHRISTIAN;TEICH JUERGEN |
分类号 |
H03K19/177;G06F17/50 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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