ALL-DIGITAL SELECTABLE DUTY CYCLE GENERATION

摘要

All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block (210) is provided for computing the product of a selected duty cycle (C) and a discrete ratio (L) between a reference clock period and a high-frequency oscillator period. The computation block (210) may be coupled to a pulse width generator (220) for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period (Tosc). In another aspect, a pulse width generator (220) may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.