发明名称 CLOCK DATA REPRODUCTION CIRCUIT, REPRODUCING METHOD, AND STATION SIDE DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock data reproduction circuit capable of preventing the occurrence of a phenomenon in which a reference clock signal and a frequency temporarily collapse greatly when coming into a non-signal section between burst signals; and to provide a reproducing method, and a station-side device using the reproduction circuit. <P>SOLUTION: A frequency multiplication part 110 multiplies the frequency of the reference clock signal to a frequency corresponding to a data signal to be a multiplied clock signal, and uses an input selecting part 111 to selects an input. That is, when a burst signal as a data signal is input, a reproduction clock signal is generated so as to synchronize a phase with the input burst signal, and when the burst signal is not input, the reproduction clock signal is generated so as to synchronize a phase with the multiplied clock signal. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010258678(A) 申请公布日期 2010.11.11
申请号 JP20090105220 申请日期 2009.04.23
申请人 SUMITOMO ELECTRIC IND LTD 发明人 UMEDA DAISUKE
分类号 H04L7/033;H03L7/08;H03L7/10 主分类号 H04L7/033
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