发明名称 DATA PROCESSING APPARATUS
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a data processing apparatus for preventing the overflow and underflow of an FIFO. <P>SOLUTION: An arithmetic engine 2 (21) performs arithmetic processing to data stored in an FIFO2 (22) for RD, and stores an arithmetic result in an FIFO2 (23) for WR. When a data readout request from the FIFO2 (22) for RD and a data write-in request from an FIFO2 (23) for WR are issued, an REQ issue control part 24a preferentially issues the data readout request when the number of valid data stored in the FIFO2 (22) for RD is less than a lower limit value set by a priority control condition setting register 26. Also, when the number of valid data stored in the FIFO2 (23) for WR exceeds the upper limit value set by the priority control condition setting register 26, the REQ issue control part 24a preferentially issues a data write-in request. Thereby, it becomes possible to prevent the overflow and underflow of the FIFO. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2010257128(A) 申请公布日期 2010.11.11
申请号 JP20090105321 申请日期 2009.04.23
申请人 RENESAS ELECTRONICS CORP 发明人 SUZUKI AKIRA;NOGAMI YOJI
分类号 G06F12/00;G06F13/38 主分类号 G06F12/00
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