| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a receiving apparatus which can reduce a circuit scale and is easy in speed-up. <P>SOLUTION: A receiving apparatus 1 which receives serial data, includes a sampler unit 10, an edge detection unit 20, a logical OR operation unit 31, a timing determining unit 40, a register unit 51, a selector unit 60, and a latch unit 70. The edge detection unit 20 receives data OSD[n] outputted from the sampler unit 10 as input, performs an exclusive-OR operation between the data OSD[n] and data OSD[n+1] adjoining each other, and outputs the result of the exclusive-OR operation, that is, data EDG[n]. The logical OR operation unit 31 receives the data EDG[n] outputted from the edge detection unit 20 as input, performs a logical disjunction of the sets of data EDG[n] over a predetermined period with respect to each n having a remainder of m when a difference (n-n<SB>0</SB>), where n<SB>0</SB>is a reference value, is divided by a value M, and outputs the result of the logical OR operation, that is, data EDGFLG[m]. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
