| 摘要 |
A memory arrangement comprises a first memory transistor (11) for non-volatile storage of a first bit, a second memory transistor (17) for non-volatile storage of the first bit in inverted form, and a word line (29) that is connected to a control terminal (12) of the first memory transistor (11) and a control terminal (18) of the second memory transistor (17). The memory arrangement further comprises a read amplifier (23) with a first input (24) that is coupled to the first memory transistor (11) for supplying a first bit line signal (BL1), a second input (25) that is coupled to the second memory transistor (17) for supplying a second bit line signal (BL2), and an output (26) for provision of an output signal (SOUT) as a function of the first bit line signal (BL1) and the second bit line signal (BL2).
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