SEMICONDUCTOR MEMORY DEVICE

摘要

A semiconductor memory device provided with memory cells (100) arranged at the intersections between word lines and bit lines, pre-charge circuits (101) connected to the bit lines, column selection circuits (102) controlled by write control signals, and a clamp circuit (103A) provided as a write circuit. The clamp circuit (103A) comprises a transistor (QN17) which controls the potential of a selected bit line to a first potential (for example, 0V), and a variable capacitance element (C11) which controls the potential of the selected bit line to a second potential (for example, a negative potential) lower than the first potential. Because a variable capacitance element (C11) is employed, in cases when the power supply voltage is high, the element capacitance can be reduced, thereby suppressing the amount of drop from the first potential to the second potential.