发明名称 METHOD FOR SUPPRESSING RESONANCE OF POWER PLANE IN PRINTED CIRCUIT BOARD
摘要 <p><P>PROBLEM TO BE SOLVED: To achieve a proper capacitor arrangement method when resonance occurs in a power plane in a printed circuit board in which a power plane and a ground plane are provided and the power plane and the ground plane are connected by a capacitor. <P>SOLUTION: The method is configured to suppress the resonance of the power plane in the printed circuit board in which the power plane and a ground plane are provided. A capacitor, in which an impedance at a resonance frequency of the power plane shows a minimum value, is installed at a point near the part, where resonance occurs, of the power plane so as to connect the power plane and the ground plane to each other. A resistor is connected in series to the capacitor. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2010251373(A) 申请公布日期 2010.11.04
申请号 JP20090096114 申请日期 2009.04.10
申请人 AICA KOGYO CO LTD 发明人 NOZAKI TAKAHIDE;IKEDA SATOSHI
分类号 H05K3/46 主分类号 H05K3/46
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