发明名称 SEMICONDUCTOR DEVICE
摘要 <p>In order to reduce memory power consumption during operation and standby, a memory block (MB) including a variable resistance memory element comprises: an address transformation circuit (ATC) for performing a conversion between a logical address and a physical address on the basis of an address transformation table (ATT); and a bank control circuit (BCC) for individually controlling the power supplies to memory banks (BANK). The ATC performs the address conversion, for example, so that external memory accesses are localized to a specific BANK. Consequently, an unused BANK can be secured and the power supply to the periphery circuit of the unused BANK can be blocked through the BCC.</p>
申请公布号 WO2010125852(A1) 申请公布日期 2010.11.04
申请号 WO2010JP53397 申请日期 2010.03.03
申请人 HITACHI, LTD.;ONO, KAZUO;KAWAHARA, TAKAYUKI;SEKIGUCHI, TOMONORI;NAGAI, YASUSHI 发明人 ONO, KAZUO;KAWAHARA, TAKAYUKI;SEKIGUCHI, TOMONORI;NAGAI, YASUSHI
分类号 G11C13/00 主分类号 G11C13/00
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