发明名称 METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To achieve electric inspection of a semiconductor integrated circuit device having a test pad with narrowed pitches. SOLUTION: A semiconductor wafer partitioned into a plurality of chip domains in which a semiconductor integrated circuit is formed respectively, and having a plurality of electrodes connected electrically to the semiconductor integrated circuit and formed on a main surface, is prepared, and tips of a plurality of contact terminals are brought into contact with the plurality of electrodes by using a probe card having the plurality of contact terminals contactable with the plurality of electrodes. The probe card includes a first sheet (2) including the contact terminals and second wiring electrically connected thereto, and a second sheet (45) by an invar is arranged on the back surface of a domain therein where the contact terminals are formed. On the second sheet, a first elastomer is provided penetratingly through the second sheet on a formation position of the contact terminals, and a second elastomer is provided penetratingly through the second sheet on a position in the periphery of the first elastomer. A domain where the contact terminals are formed on the first sheet is pressed from the back surface through the second sheet, to thereby bring the tips of the contact terminals into contact with the electrodes. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010249841(A) 申请公布日期 2010.11.04
申请号 JP20100170372 申请日期 2010.07.29
申请人 RENESAS ELECTRONICS CORP 发明人 OKAMOTO MASAYOSHI;MATSUMOTO HIDEYUKI;YORISAKI SHINGO;HASEBE AKIO;MOTOYAMA YASUHIRO;SHIMASE AKIRA
分类号 G01R1/073;H01L21/66 主分类号 G01R1/073
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