| 摘要 |
PROBLEM TO BE SOLVED: To concurrently solve the following problems: low yield due to over kill, an increase in a chip area due to an excessive margin, an increase in power consumption, and a long designing period. SOLUTION: The test pattern generator 10 is equipped with: an input part 12 for receiving inputs of a network list including connection information of a plurality of cells of a semiconductor integrated circuit, cell data including position information of the respective cells and wiring information of wires connected to the respective cells, cell power data including power consumption of the respective cells and target power supply voltage data including a target power supply voltage; an activation rate setting part 14a for setting a cell activation rate; a test pattern generation part 14b for generating a test pattern, based on the activation rate set by the activation rate setting part 14a; a power supply voltage calculation part 14c for calculating a power supply voltage of a semiconductor integrated circuit, using the test pattern generated by the test pattern generation part 14b; and an output part 18 for outputting the test pattern generated by the test pattern generation part 14b. COPYRIGHT: (C)2011,JPO&INPIT
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