| 摘要 |
The present invention relates to a tri-state delay-typed phase lock loop, which comprises: a phase and frequency detector, a mode detector, a mode selector, a first sampling delay unit, a plurality of counters, a second sampling delay unit, and a phase and frequency calculator. The phase and frequency of the input reference signal can be determined automatically by the phase lock loop, and the output synchronization signal can be generated such that the frequency and the phase of the output synchronization signal are identical to those of the input reference signal.
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