| 摘要 |
<P>PROBLEM TO BE SOLVED: To prevent deterioration in an operation margin of a memory cell in which complementary storage nodes are short-circuited during write operation. <P>SOLUTION: A semiconductor memory has a short transistor coupling complementary storage nodes of a latch circuit of a memory cell. A transfer transistor and the short transistor have a diffusion layer in common coupled to one of the storage nodes. The short transistor and a driver transistor have a diffusion layer in common coupled to the other storage node. The transfer transistor, the short transistor and the driver transistor are continuously disposed via the diffusion layers in common, and thereby, variation of characteristics of the transfer transistor can be prevented. Accordingly, it may be possible to prevent that current supplying ability of the transfer transistor changes depending on a layout in the memory cell. <P>COPYRIGHT: (C)2011,JPO&INPIT |
