发明名称 Dual Interconnection in Stacked Memory and Controller Module
摘要 A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.
申请公布号 US2010270668(A1) 申请公布日期 2010.10.28
申请号 US20090431569 申请日期 2009.04.28
申请人 WAFER-LEVEL PACKAGING PORTFOLIO LLC 发明人 MARCOUX PHIL P.
分类号 H01L23/48;H01L21/50;H01L21/762;H01L21/768;H01L23/52 主分类号 H01L23/48
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