发明名称 HIERARCHICAL MEMORY ARCHITECTURE TO CONNECT MASS STORAGE DEVICES
摘要 PROBLEM TO BE SOLVED: To cope with additional improvements needed at an interface to a mass-storage memory device. SOLUTION: A hierarchical memory storage uses a concentrator device that is located between a processor and memory storage devices to provide a series of memory devices and enables attachment of a memory depth to a processor controller with a limited pin count. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010244553(A) 申请公布日期 2010.10.28
申请号 JP20100095441 申请日期 2010.03.31
申请人 EILERT SEAN 发明人 EILERT SEAN
分类号 G06F13/16 主分类号 G06F13/16
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