发明名称 Semiconductor device and layout method therefor
摘要 Provided is a semiconductor device including: an MIM capacitor that includes a lower electrode, an upper electrode, and a capacitor insulating film formed between the lower electrode and the upper electrode; a first via hole that connects to the lower electrode and extends in a normal upward direction of a principal surface of the lower electrode; a second via hole that connects to the upper electrode and extends in a normal upward direction of a principal surface of the upper electrode; and a plurality of lower wiring lines that are formed under the lower electrode, in which formation areas of the first and second via holes overlap formation areas of the plurality of lower wiring lines when viewed in the normal direction of the principal surface of the upper electrode.
申请公布号 US2010270643(A1) 申请公布日期 2010.10.28
申请号 US20100662149 申请日期 2010.04.01
申请人 NEC ELECTRONICS CORPORATION 发明人 IWAKI TAKAYUKI
分类号 H01L29/92;H01L21/02 主分类号 H01L29/92
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