发明名称 PEAK HOLD CIRCUIT WITH DROOP CORRECTION
摘要 PROBLEM TO BE SOLVED: To provide a peak hold circuit with droop correction capable of holding a peak voltage for a long time by suppressing the droop in the peak hold circuit. SOLUTION: A hold capacitor C1 of the peak hold circuit is constituted so that one end is connected to a cathode of a diode D1 and another end is connected to the droop correction circuit 20. The droop correction circuit 20 applies a holding voltage of a hold capacitor C2 to the hold capacitor C1 by inverting a polarity in an amplifier circuit A3. That is, the droop correction circuit 20 applies a droop correction voltage to the hold capacitor C1, which has a polarity reversed to that of a holding voltage of the holding capacitor C1. By applying the droop correction voltage, the droop of the hold capacitor C1 is suppressed for a long time. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010244610(A) 申请公布日期 2010.10.28
申请号 JP20090091619 申请日期 2009.04.04
申请人 MARKTEC CORP 发明人 HIBINO TAKASHI
分类号 G11C27/00;H03K17/00 主分类号 G11C27/00
代理机构 代理人
主权项
地址