| 摘要 |
An output driver comprising low voltage transistors provides high voltage logic outputs. During a high-to-low output transition the source voltage of the cascode transistor 120 is rapidly reduced by the NMOS pull-down device 125, but the drain potential remains high until the output node 130 discharges, resulting in an excessive drain-source voltage across the cascode transistor 120. To improve transient voltage distribution across the output transistors 120,125 and so reduce gate breakdown and hot carrier injection effects, the gate bias for cascode transistor 120 is temporarily raised (170,160,155,165) during a high-to-low output transition. The voltage at the source of cascode transistor 120 may be limited by a source follower clamp. Analogous techniques may be used in the pull-up circuit (figures 5 and 6), the source follower clamp assisting turn-on of the PMOS cascode device (415, figure 6). |
