发明名称 Data processor and control system
摘要 Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.
申请公布号 US7822899(B2) 申请公布日期 2010.10.26
申请号 US20080044667 申请日期 2008.03.07
申请人 RENESAS ELECTRONICS CORPORATION 发明人 OYAMA HIDEMI;KAWAMURA MASANOBU;IKEGUCHI TAKUYA;MATSUMOTO MASANORI;KAWAJIRI HIROYUKI
分类号 G06F13/24;G06F3/00 主分类号 G06F13/24
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