| 摘要 |
A device comprises a first circuit that generates a first phase component and a second phase component. A pipelined analog to digital converter comprises N stages, wherein N is an integer greater than one. At least one of the N stages includes a sample and integrate circuit that selectively samples the first phase component and integrates a sampled second phase component to generate an integrated second phase component during one portion of a first clock phase of the sample and integrate circuit, and that selectively integrates the sampled first phase component to generate an integrated first phase component and samples the second phase component to generate the sampled second phase component during another portion of the first clock phase of the sample and integrate circuit.
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