发明名称 |
Integrated decision feedback equalizer and clock and data recovery |
摘要 |
In an integrated decision feedback equalizer and clock and data recovery circuit one or more flip-flops and/or latches may be shared. One or more flip-flops and/or latches may be used in retiming operations in a decision feedback equalizer and in phase detection operations in a clock recovery circuit. Outputs of the flip-flops and/or latches may be used to generate feedback signals for the decision feedback equalizer. The output of a flip-flop and/or latches may be used to generate signals that drive a charge pump in the clock recovery circuit.
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申请公布号 |
US7822113(B2) |
申请公布日期 |
2010.10.26 |
申请号 |
US20040823252 |
申请日期 |
2004.04.13 |
申请人 |
BROADCOM CORPORATION |
发明人 |
TONIETTO DAVIDE;MOMTAZ AFSHIN |
分类号 |
H03H7/30;H03L7/08;H03L7/089;H03L7/091;H04L7/02;H04L7/033;H04L25/03 |
主分类号 |
H03H7/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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