发明名称 Semiconductor memory
摘要 Address comparison circuits each compare the defect addresses programmed in the redundancy fuse circuits with an access address and output a redundancy signal when a comparison result is a match. A switch circuit is controlled to switch according to a redundancy selection signal output from a selection fuse circuit, and validates in response to the redundancy signal either a corresponding regular redundancy line or the reservation redundancy line. By dividing the redundancy lines into the regular redundancy lines and the reservation redundancy line, each of the redundancy fuse circuits can be made to correspond to one of the plurality of redundancy lines with the simple switch circuit. Therefore, a difference in propagation delay time of a signal can be made small and a difference in access time can be made small between when relieving a defect and when there is no defect.
申请公布号 US7821854(B2) 申请公布日期 2010.10.26
申请号 US20080239452 申请日期 2008.09.26
申请人 FUJITSU SEMICONDUCTOR LIMITED 发明人 KOBAYASHI HIROYUKI
分类号 G11C29/00 主分类号 G11C29/00
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