发明名称 HARDWARE PROCESS TRACE FACILITY
摘要 A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data.
申请公布号 US2010268995(A1) 申请公布日期 2010.10.21
申请号 US20090425075 申请日期 2009.04.16
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 GOODMAN BENJIMAN L.;CAKICI SERTAC;WARD SAMUEL I.;WARD, JR. LINTON B.
分类号 G06F11/07 主分类号 G06F11/07
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