发明名称 PACKET PROCESSING APPARATUS AND INTERFACE UNIT
摘要 <p><P>PROBLEM TO BE SOLVED: To enable high-speed packet switching at the time of failure, even in a broadband network. <P>SOLUTION: A packet processing apparatus includes a plurality of IF units each connected with a counter apparatus via a work path or a protection path and an SW connecting the plurality of IF units via a data bus. When a packet sent from the counter apparatus is received by any one of the plurality of IF units, the packet processing apparatus determines whether the packet is a monitoring packet monitoring a connection state with the counter apparatus. When it is determined that the packet is a monitoring packet, the packet processing apparatus uses the data bus via the SW to transmit the monitoring packet to the plurality of IF units. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2010239593(A) 申请公布日期 2010.10.21
申请号 JP20090088236 申请日期 2009.03.31
申请人 FUJITSU LTD 发明人 YATANI KOJI;EBARA TETSUO;MIMORI YASUYUKI;YAMAMOTO KANTA;KAWAGUCHI JUNICHI;KATSURA YUICHIRO
分类号 H04L12/26;H04L12/70;H04L12/707;H04L12/711 主分类号 H04L12/26
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