发明名称 PIPE LATCH CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a pipe latch circuit which is initialized each time read operation is terminated and allows input/output sequence of data latched in a pipe latch to be always matched, and to provide a semiconductor memory device using the same. SOLUTION: The pipe latch circuit includes: a reset signal-generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled after all data are output to an outside upon read operation or upon entry into the write operation; an input/output control signal-generating unit which generates many input control signals and output control signals in response to a read strobe signal and a clock signal, and is initialized in response to the reset signal; and a pipe latch unit which latches input data in response to the input control signals and outputs the latched data in response to the output control signals. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010238347(A) 申请公布日期 2010.10.21
申请号 JP20090171041 申请日期 2009.07.22
申请人 HYNIX SEMICONDUCTOR INC 发明人 KIM YOUK HEE;KO BOK RIM;KIM YOUNG JOO
分类号 G11C11/409;G11C11/407;G11C11/4076;H03K3/356;H03K17/22 主分类号 G11C11/409
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