| 摘要 |
PROBLEM TO BE SOLVED: To provide a DLL circuit that achieves further improvement in jitter accuracy by suppressing variations in gain setting of an amount of change of a lock frequency with respect to changes in LPF output. SOLUTION: The DLL circuit includes: a delay circuit 101 for generating a delay clock; a phase comparator circuit 10 for outputting a phase-difference signal between the delay clock and an input clock; a charge pump circuit 20 for outputting a phase-difference voltage corresponding to the phase-difference signal; a low-pass filter circuit 30 for removing a high-frequency component of the output of the charge pump circuit; and a delay control circuit 102 that includes a first voltage-current converting circuit 40 for converting an output voltage of the low-pass filter circuit into a current, a second voltage-current converting circuit 50 for converting a reference voltage Vref into a current, includes a voltage obtained by converting the result obtained by subtracting an output current of the second voltage-current converting circuit from an output current of the first voltage-current converting circuit and a voltage obtained by converting an offset current Id, and outputs the voltage obtained by converting the offset current to the delay circuit as a control voltage Vcont when the phase-difference voltage is smaller than the reference voltage. COPYRIGHT: (C)2011,JPO&INPIT
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