<p>The invention relates to a memory element consisting of an MOS transistor having a drain (8), a source (7) and a body region covered by an insulated gate (12), wherein the thickness of the body region is divided into two distinct regions (13, 14) separated by a portion of an insulating layer (16) extending parallel to the plane of the gate.</p>
申请公布号
WO2010119224(A1)
申请公布日期
2010.10.21
申请号
WO2010FR50716
申请日期
2010.04.13
申请人
CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE;UNIVERSIDAD DE GRANADA;CRISTOLOVEANU, SORIN, IOAN;RODRIGUEZ, NOEL;GAMIZ, FRANCISCO
发明人
CRISTOLOVEANU, SORIN, IOAN;RODRIGUEZ, NOEL;GAMIZ, FRANCISCO
