发明名称 Means to reduce the PLL phase bump caused by a missing clock pulse
摘要 A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.
申请公布号 US7816958(B2) 申请公布日期 2010.10.19
申请号 US20070744420 申请日期 2007.05.04
申请人 EXAR CORPORATION 发明人 SUNDBY JAMES TONER
分类号 H03L7/06 主分类号 H03L7/06
代理机构 代理人
主权项
地址