| 摘要 |
A PLL frequency generator is disclosed for generating an output signal with a settable target frequency, comprising a) a voltage-controlled oscillator for generating the output signal, b) a switchable frequency divider, which is connected to the voltage-controlled oscillator and is designed to derive from the output signal a frequency-divided signal whose instantaneous frequency depends on a value of an adjustable divisor, c) a switchable delay unit, which is connected to the frequency divider and is designed to generate a delayed signal in that the frequency-divided signal is delayed by delay times that depend on a control word, and d) a controller connected to the switchable delay unit controller and designed to determine the control words. According to the invention, the controller has a sigma-delta modulator and is designed to determine the control words depending on at least one signal provided by the sigma-delta modulator.
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