| 摘要 |
A yield of a semiconductor layout may be improved by selecting a pattern that does not satisfy at least one of multiple rules within the layout, adding a margin to a predetermined value of the at least one of the rules associated with selected pattern, based on a ground rule and a recommended rule of each of the rules, calculating an overall fail rate of at least one of the rules that varies according to the addition of the margin, and determining an adjusted margin to be added based on the calculated overall fail rate.
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