发明名称 Clock circuit for reducing long term jitter
摘要 A clock circuit generates a reference clock signal based on a resonant frequency of a crystal, generates thermometer-coded signals based on the reference clock signal, and generates a pulse train based on the thermometer-coded signals. The pulse train has a frequency that is a multiple of the frequency of the reference clock signal. Additionally, the clock circuit includes a phase-lock loop for generating an output clock signal based on the pulse train and aligning a phase of the output clock signal with pulses in the pulse train. In various embodiments, the frequency of the reference clock signal is the same as the resonant frequency of the crystal and the frequency of the output clock signal is a multiple of the resonant frequency of the crystal. Moreover, reference clock signal and the output clock signal each have a long-term jitter based on the precision of the resonant frequency of the crystal.
申请公布号 US7816959(B1) 申请公布日期 2010.10.19
申请号 US20090391105 申请日期 2009.02.23
申请人 INTEGRATED DEVICE TECHNOLOGY, INC. 发明人 ISIK TACETTIN
分类号 H03L7/06 主分类号 H03L7/06
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