| 摘要 |
A level shifter circuit is disclosed. The circuit receives a digital input signal characterized by a logical high state having a first high voltage level and generates an output node for driving a digital output signal characterized by a logical high state having a second high voltage level. The output signal logical state mirrors the input signal logical state. The circuit includes a short circuit current reduction mechanism for charging a first internal node of level shifter circuit following a first transition of the input signal logical state. The circuit further includes a performance enhancement mechanism for discharging the first internal node of the level shifter circuit following a second transition of the input signal logical state. The performance enhancement mechanism may comprise a transistor driven by the input signal and connected between the first internal node and ground. The current limiting mechanism may comprise a transistor having a source/drain terminal connected to the first internal node.
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