发明名称 Segmented pillar layout for a high-voltage vertical transistor
摘要 In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
申请公布号 US7816731(B2) 申请公布日期 2010.10.19
申请号 US20090321250 申请日期 2009.01.20
申请人 POWER INTEGRATIONS, INC. 发明人 PARTHASARATHY VIJAY;GRABOWSKI WAYNE BRYAN
分类号 H01L29/78 主分类号 H01L29/78
代理机构 代理人
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