发明名称 Processor system management mode caching
摘要 In some embodiments, an apparatus comprises one or more processors supporting a system management mode, system management memory, and software controllable caching of memory, one or more memory modules, a memory controller, and a communication bus to couple the one or more memory modules to the memory controller. Other embodiments may be described.
申请公布号 US7818496(B2) 申请公布日期 2010.10.19
申请号 US20070731755 申请日期 2007.03.30
申请人 INTEL CORPORATION 发明人 COOPER BARNES;ORAM ISAAC;BRANNOCK KIRK;GOUGH ROBERT
分类号 G06F13/00;G06F12/00 主分类号 G06F13/00
代理机构 代理人
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