发明名称 CACHE MEMORY DEVICE, CACHE MEMORY CONTROL METHOD, PROGRAM, AND INTEGRATED CIRCUIT
摘要 <p>A cache memory device performs a line size determination process to determine a line size to be refilled, prior to a refill process performed at the time of a cache miss. In the line size determination process, read/write numbers of management target lines which belong to a set are acquired (S51); when all read numbers are identical and all write numbers are identical (S52: Yes), the line size to be refilled is determined to be a large size (S54); when not all of the read numbers or not all of the write numbers are identical (S52: No), the line size to be refilled is determined to be a small size (S55).</p>
申请公布号 WO2010116735(A1) 申请公布日期 2010.10.14
申请号 WO2010JP02551 申请日期 2010.04.07
申请人 PANASONIC CORPORATION;KATO, KAZUOMI 发明人 KATO, KAZUOMI
分类号 G06F12/08 主分类号 G06F12/08
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