发明名称 |
METHOD OF VERIFYING THE PERFORMANCE MODEL OF AN INTEGRATED CIRCUIT |
摘要 |
A method of verifying a performance model of an integrated circuit is provided. The method comprises the following steps: obtaining statistical request numbers and corresponding latency values of memory access requests; developing functions of latency value based on the statistical request numbers and the corresponding latency values; bringing a random value to one of the functions to retrieve a latency value; and verifying the logic of the performance model using the latency value retrieved in the step above.
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申请公布号 |
US2010262415(A1) |
申请公布日期 |
2010.10.14 |
申请号 |
US20090638865 |
申请日期 |
2009.12.15 |
申请人 |
NVIDIA CORPORATION |
发明人 |
NASH REUEL WILLIAM;BAI YU;LI XIAOWEI |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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