| 摘要 |
A processor comprising one or more control units, a plurality of first execution units, and one or more second execution units. Fetched instructions that conform to a processor instruction set are dispatched to the first execution units. Fetched instructions that conform to a second instruction set (different from the processor instruction set) are dispatched to the second execution units. The second execution units may be configured to performing graphics operations, or other specialized functions such as executing Java bytecode, managed code, video/audio processing operations, encryption/decryption operations etc. The second execution units may be configured to operate in a coprocessor-like fashion. A single control unit may handle the fetch, decode and scheduling for all the executions units. Alternatively, multiple control units may handle different subsets of the executions units. |
