发明名称 Row expansion reduction by inversion for range representation in ternary content addressable memories
摘要 A method and circuit to implement a match against range rule functionality. A first rule entry and a second rule entry are stored. The first rule entry includes at least two consecutive identical bits. The first rule entry represents a numerical range. A first field of a binary key is compared with the first rule entry to determine whether any of the bits of the first field are not identical. A logical result of the comparison between the first field and the first rule entry is inverted to generate a first comparison result. A second field of the binary key is compared with a second rule entry to generate a second comparison result. The first comparison result is then logically ANDed with the second comparison result to determine whether the binary key falls within the numerical range represented by the first rule entry and matches the second rule entry.
申请公布号 US7814268(B2) 申请公布日期 2010.10.12
申请号 US20080072361 申请日期 2008.02.25
申请人 NETLOGIC MICROSYSTEMS, INC. 发明人 MAHESHWARI DINESH
分类号 G06F12/00 主分类号 G06F12/00
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