发明名称 Method for reducing power consumption in a volatile memory and related device
摘要 A method for reducing power consumption in a volatile memory includes switching off a bitline voltage provider according to a leakage control signal when a bitline array corresponding to the bitline voltage provider is dysfunctional due to a wordline to bitline short, controlling connections between a plurality of first bitline arrays corresponding to the bitline voltage provider and a plurality of sense amplifiers according to an access control signal, controlling connections between a plurality of second bitline arrays corresponding to the plurality of first bitline arrays and the plurality of sense amplifiers according to the access control signal, and providing power to the plurality of corresponding sense amplifiers according to the access control signal.
申请公布号 US7813209(B2) 申请公布日期 2010.10.12
申请号 US20080243944 申请日期 2008.10.01
申请人 NANYA TECHNOLOGY CORP. 发明人 PARENT RICHARD MICHAEL
分类号 G11C5/14;G11C7/00 主分类号 G11C5/14
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