发明名称 Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access
摘要 A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
申请公布号 US7814300(B2) 申请公布日期 2010.10.12
申请号 US20080112583 申请日期 2008.04.30
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 MOYER WILLIAM C.;SCOTT JEFFREY W.
分类号 G06F9/38 主分类号 G06F9/38
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