| 摘要 |
The present invention provides a data cache architecture interposed between a host and a flash memory, the data cache architecture comprising: a buffer memory, receiving data from the host; a memory controller, deploying the data in the buffer memory; and a data cache memory, controlled by the memory controller according to a cache algorithm. The data cache architecture and the cache algorithm used in the data cache architecture can be used to minimize the program/erase count of the NAND type flash device.
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