CLOCK SIGNAL GENERATOR CIRCUIT FOR REDUCEING CURRENT CONSUMPTION, AND SEMICONDUCTOR DEVICE HAVING THE SAME

摘要

PURPOSE: A clock signal generating circuit and a semiconductor device are provided to stabilize an operation by generating a latency control clock and an inner read command signal through the same clock domain. CONSTITUTION: A signal generation circuit(110) generates a first clock signal divided from an external clock signal. A determining unit(140) compares the phase of the first clock signal with the phase of the control clock signal. The determining unit outputs a clock signal with the same phase as or opposite phase to the first clock signal. A latency control clock signal generator(120) generates a first latency control clock signal by delaying the clock signal. A latency generator(150) controls the latency of the inner read command signal.