| 摘要 |
A power MOSFET wafer level chip-scale packaging method is disclosed. The method includes the steps of electroless plating a wafer backside and a plurality of contact pads on a wafer front side and forming solder balls on the plated plurality of contact pads before dicing the wafer into a plurality of power MOSFET dies. In an alternative embodiment, the method includes the steps of providing a permanent protective layer on a wafer backside, electroless plating a plurality of contact pads on a wafer front side, and forming solder balls on the plated plurality of contact pads before dicing the wafer into a plurality of power MOSFET dies. |
