发明名称 System timeline execution model development methodology for large distributed real-time embedded systems
摘要 The present invention is a project management tool uniquely suited to define and develop significant system events that can be effectively used as system test points to measure the performance and determine whether the system under design is meeting key design requirements. This methodology utilizes Synch Points in a state diagram to provide a directed graph notation and to generate a system timeline execution model automatically. The state diagram provides an improved means to decompose system event times into mechanical motion times, move transition latency times, and application software latency times. The system timeline execution model data is fed into a simulation engine to verify that the system timeline execution model is executable and confirms the dependencies are complete and accurate.
申请公布号 US2010257106(A1) 申请公布日期 2010.10.07
申请号 US20060527740 申请日期 2006.09.26
申请人 IYER BALASUBRAMANIAN K;LARSON PHYLLIS J 发明人 IYER BALASUBRAMANIAN K.;LARSON PHYLLIS J.
分类号 G06Q10/00 主分类号 G06Q10/00
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