CLOCK GLITCH DETECTION

摘要

A circuit comprises a clock tree (714) for distributing a clock signal. A first counter (718) is arranged at a first point (724) in the clock tree. Upon detecting a triggering edge in the clock signal, the first counter sets a first current count equal to a first delayed count. After a first delay, the first counter sets the first delayed count equal to the first current count plus an increment. A second counter (720) is arranged at a second point (726) in the clock tree. Upon detecting a triggering edge in the clock signal, the second counter sets a second current count equal to a second delayed count. After a second delay, the second counter sets the second delayed count equal to the second current count plus the increment. A comparator (722) compares the first current count and the second current count. The first point (724) and the second point (726) are not the same, or the second delay is longer than the first delay.