发明名称 INTERFACE CIRCUIT
摘要 A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.
申请公布号 US2010257324(A1) 申请公布日期 2010.10.07
申请号 US20100751810 申请日期 2010.03.31
申请人 RENESAS TECHNOLOGY CORP. 发明人 OSAWA TOKUYA;HARAGUCHI MASARU;MOROOKA YOSHIKAZU;KINOSHITA HIROSHI
分类号 G06F12/00 主分类号 G06F12/00
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