| 摘要 |
PROBLEM TO BE SOLVED: To shorten a cycle time by stably compressing timing margin of read-out in an SRAM module for variation in manufacturing and use environment change. SOLUTION: An SRAM module 1 has such constitution that the module 1 has a bit cells 11 arranged in a N rows×M columns SRAM array 10 and a replica SRAM cell columns of replica bit cells 21 utilized for measurement of performance and the number of replica bit cells utilized for measurement of performance can be controlled, When an inside pulse 70 is generated in a clock generator circuit 50 by receiving a clock, a front edge of the pulse is made by the clock (clk), a trailing edge of the pulse is generated by a delay circuit including delay of the replica bit cell 21. This inside pulse 70 is used for timing control of an activation time of a word line selecting a memory cell, a bit line control circuit (bit line pre-charge circuit, an address logical circuit, and a sense amplifier). COPYRIGHT: (C)2011,JPO&INPIT |
