发明名称 Cache Optimizations Using Multiple Threshold Voltage Transistors
摘要 In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit line control circuitry that includes one or more transistors having a second nominal threshold voltage that is lower than the first nominal threshold voltage. For example, the word line driver circuit may be driven by signals from a lower voltage domain than the memory circuit's voltage domain. Lower threshold voltage transistors may be used for those signals, in some embodiments. Similarly, lower threshold voltage transistors may be used in the write data driver circuits. Other bit line control circuits may include lower threshold voltage transistors to permit smaller transistors to be used, which may reduce power and integrated circuit area occupied by the memory circuits.
申请公布号 US2010254206(A1) 申请公布日期 2010.10.07
申请号 US20090419605 申请日期 2009.04.07
申请人 CAMPBELL BRIAN J;HESS GREG M;HUANG HANG 发明人 CAMPBELL BRIAN J.;HESS GREG M.;HUANG HANG
分类号 G11C7/00;G11C8/08;G11C8/18 主分类号 G11C7/00
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