| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which suppresses degradation of a withstand voltage caused by charge unbalance between a p-type pillar layer and an n-type pillar layer. <P>SOLUTION: This method of manufacturing a semiconductor device includes processes of: forming a first conductivity type second semiconductor layer 12 on a principal surface of a first conductivity type first semiconductor layer 11; forming, on the second semiconductor layer 12, first trenches T1 having side surfaces nearly vertical to the principal surface and second trenches T2 formed on the first trenches T1 and each having a large width relative to that of the first trench T1; implanting first conductivity type impurities only into the side surfaces of the second trenches T2 from oblique directions by an ion implanting method; and forming second conductivity type third semiconductor layers 13 in the first trenches T1 and the second trenches T2 after the ion implantation to form an arrangement structure of the second semiconductor layers 12 and the third semiconductor layers 13 alternately adjacent to each other in the lateral direction nearly parallel to the principal surface. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
