发明名称 |
PROGRAMMABLE DELAY CIRCUIT WITH INTEGER AND FRACTIONAL TIME RESOLUTION |
摘要 |
<p>A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate that provides extra loading to obtain the longer delay for the second path.</p> |
申请公布号 |
EP2235823(A1) |
申请公布日期 |
2010.10.06 |
申请号 |
EP20080867868 |
申请日期 |
2008.12.18 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
KESKIN, MUSTAFA;PEDRALI-NOY, MARZIO |
分类号 |
H03K5/13 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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